A. L. PERIN, A. S. N. PEREIRA, R. T. BUHLER, M. A. G. DA SILVEIRA , R. C. GIACOMINI

IEEE TRANSACTIONS ON NUCLEAR SCIENCE

23/04/2019

Abstract

Abstract: This paper addresses a quantitative study of the reliability improvement of the stacked transistor structure. The susceptibility of integrated circuits to single-event effects caused by interaction with ionizing particles is analyzed at the semiconductor level, as well as at the device and circuit levels considering the replacement of each transistor by a stacked silicon-oninsulator (SOI) array. Up-to-date technologic nodes were used as inputs for the simulation and reliability models. A stochastic Markov model was proposed and evaluated. The model output pointed the stacked array as a real alternative for high-reliability in future applications, with exceptional results. For a 105 devicecount integrated circuit, a success probability of 80% is reached for missions over 100000 h in the commercial flights altitude, while for the single transistor system, this value is reached for missions under 100 h.

10.1109/TDMR.2019.2912862