5 de junho de 2018 | Aplicações, Publicações
L. A. Tambara, F. L. Kastensmidt, P. Rech, F. Lins, N. H. Medina, N. Added, V. A. P. Aguiar, M. A. G. Silveira
IEEE TRANSACTIONS ON NUCLEAR SCIENCE – VOL. 65, NO. 8. Data: 02 July 2018
05/06/2018
Abstract
All programmable system-on-chip (APSoC) devices provide higher system performance and programmable flexibility at lower costs compared to standalone field-programmable gate array devices and processors. Unfortunately, it has been demonstrated that the high complexity and density of APSoCs increase the system’s susceptibility to radiation-induced errors. This paper investigates the effects of soft errors on APSoCs at design level through reliability and performance analyses. We explore 28 different hardware and software co-designs varying the workload distribution between hardware and software. We also propose a reliability analysis flow based on fault injection (FI) to estimate the reliability trend of hardware-only and software-only designs and hardware-software co-designs. Results obtained from both radiation experiments and FI campaigns reveal that performance and reliability can be improved up to 117× by offloading the workload of an APSoC-based system to its programmable logic core. We also show that the proposed flow is a precise method to estimate the reliability trend of system designs on APSoCs before radiation experiments.